h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 159

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h8s-2635

Manufacturer Part Number
h8s-2635
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
4.2.4
After reset release, MSTPCRA to MSTPCRD are initialized to H'3F, H'FF, H'FF, and
B'11******
Consequently, on-chip supporting module registers cannot be read or written to. Register reading
and writing is enabled when module stop mode is exited.
Note: 1. The value of bits 5 to 0 is undefined.
4.3
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction.
Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking.
Table 4-3 shows the state of CCR and EXR after execution of trace exception handling.
Interrupts are accepted even within the trace exception handling routine.
The T bit saved on the stack retains its value of 1, and when control is returned from the trace
exception handling routine by the RTE instruction, trace mode resumes.
Trace exception handling is not carried out after execution of the RTE instruction.
Table 4-3
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
Interrupt Control Mode
State of On-Chip Supporting Modules after Reset Release
Traces
*1
Status of CCR and EXR after Trace Exception Handling
, respectively, and all modules except the DTC, enter module stop mode.
0
2
1
I
Trace exception handling cannot be used.
CCR
Rev. 6.00 Feb 22, 2005 page 99 of 1484
UI
Section 4 Exception Handling
I2 to I0
REJ09B0103-0600
EXR
T
0

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