h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 1498

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Appendix B Internal I/O Register
Rev. 6.00 Feb 22, 2005 page 1438 of 1484
REJ09B0103-0600
TCSR1—Timer Control/Status Register 1
Notes: TCSR1 register differs from other registers in being more difficult to write to. For details see section 12.2.4, Notes on Register Access.
Bit
Initial value
Read/Write
1. Only 0 can be written, to clear the flag.
2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask, W-mask versions, and
Note: * When interval timer interrupts are disabled and OVF is polled, read the OVF = 1 state at least twice.
Overflow Flag
0
1
H8S/2635 Group only.
[Clearing conditions]
• Write 0 in the TME bit (Only applies to WDT1)
• Read TCSR* when OVF = 1, then write 0 in OVF
[Setting condition]
• When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset)
Timer Mode Select
0
1
R/(W)
OVF
7
0
Interval timer mode: WDT1 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows
Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from the CPU when the TCNT overflows
*1
Timer Enable
0
1
WT/IT
TCNT is initialized to H'00 and halted
TCNT counts
R/W
6
0
Prescaler Select
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
0
1
The TCNT counts frequency-division clock pulses of the φ based prescaler (PSM)
The TCNT counts frequency-division clock pulses of the φ SUB*-based prescaler (PSS)
U-mask, W-mask versions, and H8S/2635 Group only. These functions cannot be used with
the other versions, and in them the PSS bit is reserved. Only 0 should be written to this bit.
Reset or NMI
TME
R/W
0
1
5
0
NMI request
Internal reset request
Clock Select 2 to 0
Notes: 1. An overflow period is the time interval between the start of counting up
PSS
PSS
0
0
1
R/W
4
0
2. Subclock functions (subactive mode, subsleep mode, and watch mode)
CKS2
*2
0
1
0
1
1
from H'00 on the TCNT and the occurrence of a TCNT overflow.
are available in the U-mask, W-mask versions, and H8S/2635 Group
only, but are not available in the other versions.
RST/NMI
CKS1 CKS0
R/W
0
1
0
1
0
1
1
0
1
3
0
H'FFA2(W), H'FFA2(R)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CKS2
R/W
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
φSUB/2
φSUB/4
φSUB/8
φSUB/16
φSUB/32
φSUB/64
φSUB/128
φSUB/256
2
0
Clock
*2
*2
*2
*2
*2
*2
*2
*2
CKS1
R/W
1
0
Overflow Period
(where φSUB
CKS0
R/W
0
0
25.6 µs
819.2 µs
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
15.6 ms
31.3 ms
62.5 ms
125 ms
250 ms
500 ms
1 s
2 s
*1
*2
(where φ = 20 MHz)
= 32.768 kHz)
WDT1