HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 130
HD6417705F133BV
Manufacturer Part Number
HD6417705F133BV
Description
MPU 3V 0K PB-FREE 208 FP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417705F133BV.pdf
(741 pages)
Specifications of HD6417705F133BV
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
105
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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3.4.3
MMU Instruction (LDTLB)
The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is
0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR
to the value specified by PTEH and PTEL, using VPN bits 16 to 12 specified in PTEH as the
index number. When the IX bit in MMUCR is 1, the EX-OR of VPN bits 16 to 12 specified in
PTEH and ASID bits 4 to 0 in PTEH are used as the index number.
Figure 3.11 shows the case where the IX bit in MMUCR is 0.
When an MMU exception occurs, the virtual page number of the virtual address that caused the
exception is set in PTEH by hardware. The way is set in the RC bit of MMUCR for each exception
according to the rules (see section 3.2.4, MMU Control Registers). Consequently, if the LDTLB
instruction is issued after setting only PTEL in the MMU exception processing routine, TLB entry
recording is possible. Any TLB entry can be updated by software rewriting of PTEH and the RC
bits in MMUCR.
As the LDTLB instruction changes address translation information, there is a risk of destroying
address translation information if this instruction is issued in the P0, U0, or P3 area. Make sure,
therefore, that this instruction is issued in the P1 or P2 area. Also, an instruction associated with an
access to the P0, U0, or P3 area (such as the RTE instruction) should be issued at least two
instructions after the LDTLB instruction.
MMUCR
31
9
0
0
SV 0 0 RC 0 TF IX AT
Way selection
Index
PTEL register
PTEH register
31 29 28
10
0
31
17
12
10 8
0
0 0
VPN
VPN
0
ASID
0
PPN
0 V 0 PR SZ C D SH 0
Write
Write
Ways 0 to 3
VPN(31-17)
VPN(11-10)
ASID(7-0)
V
PPN(28-10) PR(1-0) SZ C
D SH
0
31
Address array
Data array
Figure 3.11 Operation of LDTLB Instruction
Rev. 2.00, 09/03, page 82 of 690
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