HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 563

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 20.6 Port F Data Register (PFDR) Read/Write Operations
Note: n = 0 to 7
20.7
Port G is an 8-bit input port with the pin configuration shown in figure 20.7. Each pin has an input
pull-up MOS, which is controlled by the port G control register (PGCR) in the PFC.
20.7.1
Port G has the following register. For details on the register address and access size, see section
24, List of Registers.
PFnMD1 PFnMD0 Pin State
0
1
Bit
7 to
0
Port G data register (PGDR)
PFCR State
Bit
Name
PF7DT
to
PF0DT
Port G
Register Description
0
1
0
1
Initial
Value
0
Other function PFDR value
Output
Input (Pull-up
MOS on)
Input (Pull-up
MOS off)
Port G
R/W
R/W
Read
PFDR value
Pin state
Pin state
Figure 20.7 Port G
Description
Table 20.6 shows the function of PFDR.
PTG7 (input/output)/WAIT (input)
PTG6 (input/output)/BREQ (input)
PTG5 (input/output)/BACK (output)
PTG4 (input/output)/AUDCK (output)
PTG3 (input/output)/TRST (input)
PTG2 (input/output)/TMS (input)
PTG1 (input/output)/TCK (input)
PTG0 (input/output)/TDI (input)
Write
Data can be written to PFDR but no effect on
pin state.
Written data is output from the pin.
Data can be written to PFDR but no effect on
pin state.
Data can be written to PFDR but no effect on
pin state.
Rev. 2.00, 09/03, page 515 of 690