HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 627

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

23.4.2
Table 23.4 Reset Configuration
Notes: 1. Performs normal mode and ASE mode settings
23.4.3
The timing of data output from the TDO is switched by the command type set in the SDIR. The
timing changes at the TCK falling edge when JTAG commands (EXTEST, CLAMP, HIGHZ,
SAMPLE/PRELOAD, IDCODE, and BYPASS) are set. This is a timing of the JTAG standard.
When the UDI commands (UDI reset negate, UDI reset assert, and UDI interrupt) are set, TDO is
output at the TCK rising edge earlier than the JTAG standard by a half cycle.
A S E M D 0
H
L
2. In ASE mode, reset hold is enabled by driving the
3. ASE mode is classified into two modes; ASE break mode to execute the firm program
4. Make sure the
*
Reset Configuration
TDO Output Timing
1
A S E M D 0
A S E M D 0
constant cycle. In this state, the CPU does not start up, even if
When
The reset hold state is canceled by the following:
• Another
•
of an emulator and ASE user mode to execute the user program.
T R S T
R E S E T P
L
H
L
H
T R S T
reassert
= H, normal mode
= L, ASE mode
R E S E T P
is driven high, UDI operation is enabled, but the CPU does not start up.
T R S T
assert (power-on reset)
pin is low when the power is turned on.
T R S T
L
H
L
H
L
H
L
H
Chip State
Normal reset and UDI reset *
Normal reset *
UDI reset only
Normal operation
Reset hold *
In ASE user mode *
In ASE break mode *
masked
UDI reset only
Normal operation
R E S E T P
2
Rev. 2.00, 09/03, page 579 of 690
4
and
3
: Normal reset
3
:
R E S E T P
R E S E T P
T R S T
4
pins low for a
is driven high.
assert is