HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 595

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.2.7
BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data
specified by BDRB.
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
22.2.8
BBRB is a 16-bit readable/writable register, which specifies (1) L bus cycle or I bus cycle, (2)
instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of
channel B.
Bit
31 to 0
Bit
15 to 8
2. When the byte size is selected as a break condition, the same byte data must be set in
Break Data Mask Register B (BDMRB)
Break Bus Cycle Register B (BBRB)
bits 15 to 8 and 7 to 0 in BDRB as the break mask data in BDMRB.
Bit
Name
BDMB31 to
BDMB0
Bit
Name
Initial
Value
0
Initial
Value
0
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Description
Break Data Mask B
Specifies bits masked in the break data of channel B
specified by BDRB (BDB31 to BDB0).
0: Break data BDBn of channel B is included in the
1: Break data BDBn of channel B is masked and is not
Note: n = 31 to 0
break condition
included in the break condition
Rev. 2.00, 09/03, page 547 of 690