HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 589

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Break conditions that can be set in the UBC are
instruction fetch or data read/write access, data size, data contents, address value, and stop timing
in the case of instruction fetch.
22.1
The UBC has the following features:
UBCS311A_000020020100
The following break comparison conditions can be set.
Number of break channels: two channels (channels A and B)
User break can be requested as either the independent or sequential condition on channels A
and B (sequential break setting: channel A and then channel B match with break conditions,
but not in the same bus cycle).
User break is generated upon satisfying break conditions. A user-designed user-break
condition exception processing routine can be run.
In an instruction fetch cycle, it can be selected that a break is set before or after an instruction
is executed.
Maximum repeat times for the break condition (only for channel B): 2
Eight pairs of branch source/destination buffers.
Address (Compares 40 bits configured of the ASID and addresses 32 bits: the ASID can be
selected either all-bit comparison or all-bit mask. Comparison bits for the address are
maskable in 1-bit units; user can mask addresses at lower 12 bits (4 k page), lower 10 bits
(1 k page), or any size of page, etc.)
One of the two address buses (L bus address (LAB) and I bus address (IAB)) can be
selected.
Data (only on channel B, 32-bit maskable)
One of the two data buses (L bus data (LDB) and I bus data (IDB)) can be selected.
Bus cycle: Instruction fetch or data access
Read/write
Operand size: Byte, word, or longword
Features
Section 22 User Break Controller
Rev. 2.00, 09/03, page 541 of 690
12
– 1 times.