HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 326

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Clock
Mode
7
Notes: 1. This LSI cannot operate in an FRQCR value other than that listed in table 9.3.
Cautions:
1. The input to divider 1 is the output of the PLL circuit 1.
2. The frequency of the internal clock (I ) is:
3. The frequency of the peripheral clock (P ) is:
4.
5. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the
Rev. 2.00, 09/03, page 278 of 690
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register.
multiplication ratio of PLL circuit 1. Use the output frequency under 133.34 MHz.
1, 2, 3, or 4 can be used as the multiplication ratio of PLL circuit 1. 1, 1/2,
1/4 can be selected as the division ratios of divider 1. Set the rate in the frequency control
The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL
circuit 1, and the division ratio of divider 1.
Do not set the internal clock frequency lower than the CKIO pin frequency.
The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL
circuit 1, and the division ratio of divider 1.
The peripheral clock frequency should not be set higher than the frequency of the CKIO
pin, higher than 33.34 MHz, or lower than 13 MHz when the USB is used.
FRQCR *
H'1000
H'1001
H'1003
H'1101
H'1103
H'1111
H'1113
H'1202
H'1222
H'1303
H'1313
H'1333
2. Taking input clock frequency ratio as 1.
1
PLL1
ON ( 1)
ON ( 1)
ON ( 1)
ON ( 2)
ON ( 2)
ON ( 2)
ON ( 2)
ON ( 3)
ON ( 3)
ON ( 4)
ON ( 4)
ON ( 4)
PLL2
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Clock Rate *
(I:B:P)
1:1:1
1:1:1/2
1:1:1/4
2:1:1
2:1:1/2
1:1:1
1:1:1/2
3:1:1
1:1:1
4:1:1
2:1:1
1:1:1
2
Input Clock / Crystal
Resonator
Range
20.00 MHz to 33.34 MHz
20.00 MHz to 66.67 MHz
20.00 MHz to 66.67 MHz
20.00 MHz to 33.34 MHz
20.00 MHz to 66.67 MHz
20.00 MHz to 33.34 MHz
20.00 MHz to 66.67 MHz
26.70 MHz to 33.34 MHz
26.70 MHz to 33.34 MHz
20.00 MHz to 33.34 MHz
20.00 MHz to 33.34 MHz
20.00 MHz to 33.34 MHz
Frequency
CKIO Frequency Range
20.00 MHz to 33.34 MHz
20.00 MHz to 66.67 MHz
20.00 MHz to 66.67 MHz
20.00 MHz to 33.34 MHz
20.00 MHz to 66.67 MHz
20.00 MHz to 33.34 MHz
20.00 MHz to 66.67 MHz
26.70 MHz to 33.34 MHz
26.70 MHz to 33.34 MHz
20.00 MHz to 33.34 MHz
20.00 MHz to 33.34 MHz
20.00 MHz to 33.34 MHz
3, or