HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 609

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.3.6
1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, and interrupt
2. The values stored in BRSR and BRDR are as given below due to the kind of branch.
3. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the
exception) is generated, the branch source address and branch destination address are stored in
BRSR and BRDR, respectively.
address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read
BRSR and BRDR in order, the queue only shifts after BRDR is read. After switching the
PCTE bit (in BRCR) off and on, the values in the queues are invalid.
If a branch occurs due to a branch instruction, the address of the branch instruction is saved
in BRSR and the address of the branch destination instruction is saved in BRDR.
If a branch occurs due to an interrupt or exception, the value saved in SPC due to exception
occurrence is saved in BRSR and the start address of the exception handling routine is
saved in BRDR.
PC Trace
Rev. 2.00, 09/03, page 561 of 690