HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 36

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 6.2 Example of IRL Interrupt Connection ................................................................... 137
Figure 6.3 Interrupt Operation Flowchart............................................................................... 146
Section 7 Bus State Controller (BSC)
Figure 7.1 BSC Functional Block Diagram ............................................................................ 150
Figure 7.2 Address Space ...................................................................................................... 154
Figure 7.3 Continuous Access for Normal Space (No Wait, WM Bit in CSnWCR = 1,
Figure 7.4 Continuous Access for Normal Space (No Wait, One Wait State between Cycles) . 189
Figure 7.5 Example of 32-Bit Data-Width SRAM Connection ............................................... 190
Figure 7.6 Example of 16-Bit Data-Width SRAM Connection ............................................... 191
Figure 7.7 Example of 8-Bit Data-Width SRAM Connection ................................................. 191
Figure 7.8 Wait Timing for Normal Space Access (Software Wait Only)................................ 192
Figure 7.9 Wait State Timing for Normal Space Access
Figure 7.10
Figure 7.11 Access Timing for MPX Space (Address Cycle No Wait, Data Cycle No Wait) ... 195
Figure 7.12 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait)...... 196
Figure 7.13 Access Timing for MPX Space (Address Cycle Access Wait 1,
Figure 7.14 Example of 64-MBit Synchronous DRAM Connection (32-Bit Data Bus)............ 199
Figure 7.15 Example of 64-MBit Synchronous DRAM (16-Bit Data Bus) .............................. 200
Figure 7.16 Synchronous DRAM Burst Read Wait Specification Timing (Auto Precharge) .... 213
Figure 7.17 Basic Timing for Single Read (Auto Precharge) .................................................. 214
Figure 7.18 Basic Timing for Synchronous DRAM Burst Write (Auto Precharge).................. 216
Figure 7.19 Basic Timing for Single Write (Auto Precharge) ................................................. 217
Figure 7.20 Burst Read Timing (No Auto Precharge)............................................................. 219
Figure 7.21 Burst Read Timing (Bank Active, Same Row Address) ....................................... 220
Figure 7.22 Burst Read Timing (Bank Active, Different Row Addresses)............................... 221
Figure 7.23 Single Write Timing (No Auto Precharge)........................................................... 222
Figure 7.24 Single Write Timing (Bank Active, Same Row Address) ..................................... 223
Figure 7.25 Single Write Timing (Bank Active, Different Row Addresses)............................. 224
Figure 7.26 Auto-Refresh Timing.......................................................................................... 226
Figure 7.27 Self-Refresh Timing ........................................................................................... 227
Figure 7.28 Low-Frequency Mode Access Timing................................................................. 228
Figure 7.29 Synchronous DRAM Mode Write Timing (Based on JEDEC) ............................. 231
Figure 7.30 Burst ROM Access (Bus Width 8 Bits, Access Size 32 Bits (Number of Burst 4),
Figure 7.31 Byte-Selection SRAM Basic Access Timing ....................................................... 233
Figure 7.32 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM .............. 234
Figure 7.33 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM .............. 234
Figure 7.34 Bus Arbitration ................................................................................................... 237
Rev. 2.00, 09/03, page xxxiv of xlvi
16-Bit Bus Width, Longword Access, No Wait State between Cycles) ................... 188
(Wait State Insertion by
C S n
Data Cycle Wait 1, External Wait 1)................................................................... 197
Access Wait for the 1st Time 2, Access Wait for 2nd Time and after 1)............... 232
Assert Period Expansion.............................................................................. 194
W A I T
Signal).................................................................. 193