HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 506

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3. Data Stage (Control-Out)
The application first analyzes command data from the host in the setup stage, and determines the
subsequent data stage direction. If the result of command data analysis is that the data stage is out-
transfer, the application waits for data from the host, and after data is received (EP0oTS bit in
IFR0 = 1), reads data from the FIFO. Next, the application writes 1 to the EP0o read complete bit,
empties the receive FIFO, and waits for reception of the next data.
The end of the data stage is identified when the host transmits an IN token and the status stage is
entered.
Rev. 2.00, 09/03, page 458 of 690
Data reception from host
OUT token reception
OUT token reception
(IFR0.EP0o TS = 1)
Set EP0o reception
Figure 18.7 Data Stage (Control-Out) Operation
USB function
to TRG.EP0s
complete flag
to TRG.EP0o
1 written
1 written
RDFN?
RDFN?
Yes
Yes
ACK
NACK
NACK
No
Interrupt request
No
receive data size register
data register (EPDR0o)
(TRG.EP0o RDFN = 1)
Read data from EP0o
Read data from EP0o
Clear EP0o reception
Write 1 to EP0o read
(IFR0.EP0o TS = 0)
complete flag
complete bit
Application
(EPSZ0o)