HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 141

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4.1
Note: After power-on reset or manual reset, initialized as 16-kbyte mode (256 entries/way).
4.1.1
The cache mixes instructions and data and uses a 4-way set associative system. It is composed of
four ways (banks), and each of which is divided into an address section and a data section. Note
that the following sections will be described for the 32-kbyte mode as an example. For other cache
size modes, change the number of entries and size/way according to table 4.1. Each of the address
and data sections is divided into 512 entries. The entry data is called a line. Each line consists of
16 bytes (4 bytes
as a whole (4 ways). The cache capacity is 32 kbytes as a whole. Figure 4.1 shows the cache
structure.
Table 4.1
CACH000S_000020020300
Cache Size
16 kbytes
32 kbytes
Capacity: 16 or 32 kbytes
Structure: Instructions/data mixed, 4-way set associative
Locking: Way 2 and way 3 are lockable
Line size: 16 bytes
Number of entries: 256 entries/way in 16-kbyte mode or 512 entries/way in 32-kbyte mode
Write system: Write-back/write-through is selectable for spaces P0, P1, P3, and U0
Group 1 (P0, P3, and U0 areas)
Group 2 (P1 area)
Replacement method: Least-recently used (LRU) algorithm
Features
Cache Structure
Number of Entries and Size/Way in Each Cache Size
4). The data capacity per way is 8 kbytes (16 bytes
Number of Entries
256
512
Section 4 Cache
Rev. 2.00, 09/03, page 93 of 690
Size/Way
4 kbytes
8 kbytes
512 entries) in the cache