HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 477

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

d. Receive Data Sampling Timing and Receive Margin:
As an example, when the sampling rate is 1/16, the SCIF operates on a base clock with a
frequency of 8 times the transfer rate.
In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the
base clock. Receive data is latched at the rising edge of the fourth base clock pulse.
The receive margin can therefore be expressed as shown in equation (1).
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
M = 0.5 −
M = (0.5 – 1/(2 16)) 100% = 46.875% ........................................... (2)
M:
N:
D:
L:
F:
Receive margin (%)
Ratio of clock frequency to bit rate (N = 16)
Clock duty cycle (D = 0 to 1.0)
Frame length (L = 9 to 12)
Absolute deviation of clock frequency
2N
1
− (L − 0.5)F −
D − 0.5
N
(1 + F) × 100% ..........................
Rev. 2.00, 09/03, page 429 of 690
(1)