HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 164

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4. An exception caused by an instruction decode (General illegal instruction exceptions and slot
5. An exception related to data access (CPU address error and MMU related exceptions: re-
6. Unconditional trap (processing-completion type)
7. A user break other than one before instruction execution (processing-completion type)
8. DMA address error (processing-completion type)
Note:* If a processing-completion type exception is accepted at an instruction, exception
Only one exception is accepted at a time. Accepting multiple exceptions sequentially results in all
exception requests being processed.
Table 5.1
Exception
Type
Reset
General
exception
events
Rev. 2.00, 09/03, page 116 of 690
illegal instruction exceptions: re-execution type, unconditional trap: processing-completion
type)
execution type)
processing starts before the next instruction is executed. This exception processing
executed before an exception generated at the next instruction is detected.
Current
Instruction Exception Event
Aborted
Re-executed
Exception Event Vectors
Power-on reset
Manual reset
User break(before instruction
execution)
CPU address error (instruction
access)
TLB miss *
(instruction access)
TLB invalid *
access)
TLB protection violation *
(instruction access)
Illegal general instruction
exception
Illegal slot
instruction exception
CPU address error
(data access)
TLB miss *
(data access)
4
4
4
(instruction
4
Priority *
1
1
2
2
2
2
2
2
2
2
2
1
Exception
Order
1
2
0
1
1-1
1-2
1-3
2
2
3
3-1
Process
at BL=1
Reset
Reset
Ignored
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Vector
Code
H'A00
H'020
H'1E0
H'0E0
H'040
H'040
H'0A0
H'180
H'1A0
H'0E0/
H'100
H'040/
H'060
Vector
Offset
—
—
H'00000100
H'00000100
H'00000400
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000400