HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 21

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 1 Overview ....................................................................................... 1
1.1
1.2
1.3
1.4
Section 2 CPU ............................................................................................... 25
2.1
2.2
2.3
2.4
2.5
2.6
Section 3 Memory Management Unit (MMU) ............................................... 65
3.1
3.2
3.3
SH7705 Features.......................................................................................................... 1
Block Diagram............................................................................................................. 6
Pin Assignment............................................................................................................ 7
Pin Functions............................................................................................................... 17
Processing States and Processing Modes....................................................................... 25
2.1.1
2.1.2
Memory Map ............................................................................................................... 27
2.2.1
2.2.2
Register Descriptions ................................................................................................... 29
2.3.1
2.3.2
2.3.3
2.3.4
Data Formats ............................................................................................................... 37
2.4.1
2.4.2
Features of CPU Core Instructions ............................................................................... 40
2.5.1
2.5.2
2.5.3
Instruction Set.............................................................................................................. 48
2.6.1
2.6.2
Role of MMU .............................................................................................................. 65
3.1.1
Register Descriptions ................................................................................................... 72
3.2.1
3.2.2
3.2.3
3.2.4
TLB Functions............................................................................................................. 75
3.3.1
Processing States ............................................................................................. 25
Processing Modes............................................................................................ 26
Logical Address Space..................................................................................... 27
External Memory Space................................................................................... 28
General Registers ............................................................................................ 32
System Registers ............................................................................................. 33
Program Counter ............................................................................................. 34
Control Registers............................................................................................. 35
Register Data Format....................................................................................... 37
Memory Data Formats..................................................................................... 38
Instruction Execution Method .......................................................................... 40
CPU Instruction Addressing Modes ................................................................. 42
CPU Instruction Formats ................................................................................. 45
CPU Instruction Set Based on Functions .......................................................... 48
Operation Code Map ....................................................................................... 62
MMU of This LSI............................................................................................ 67
Page Table Entry Register High (PTEH) .......................................................... 72
Page Table Entry Register Low (PTEL) ........................................................... 73
Translation Table Base Register (TTB) ............................................................ 73
MMU Control Register (MMUCR) .................................................................. 73
Configuration of the TLB ................................................................................ 75
Contents
Rev. 2.00, 09/03, page xix of xlvi