HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 593

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.2.4
BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition
in channel B.
Bit
5
4
3
2
1
0
Bit
31 to 0
Break Address Register B (BARB)
Bit
Name
IDA1
IDA0
RWA1
RWA0
SZA1
SZA0
Bit
Name
BAB31
to
BAB0
Initial
Value
0
0
0
0
0
0
Initial
Value
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Instruction Fetch/Data Access Select A
Select the instruction fetch cycle or data access cycle as
the bus cycle of the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch cycle or data
Read/Write Select A
Select the read cycle or write cycle as the bus cycle of the
channel A break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write cycle
Operand Size Select A
Select the operand size of the bus cycle for the channel A
break condition.
00: The break condition does not include operand size
01: The break condition is byte access
10: The break condition is word access
11: The break condition is longword access
Description
Break Address B
Stores an address which specifies a break condition in
channel B.
BARB specifies the break address on LAB or IAB.
access cycle
Rev. 2.00, 09/03, page 545 of 690