HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 414

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

15.3.17 RTC Control Register 2 (RCR2)
The RTC control register 2 (RCR2) is an 8-bit readable/writable register for periodic interrupt
control, 30-second adjustment ADJ, divider circuit RESET, and RTC count start/stop control. It is
initialized to H'09 by a power-on reset. It is initialized except for RTCEN and START by a
manual reset. It is not initialized in standby mode, and retains its contents.
Rev. 2.00, 09/03, page 366 of 690
Bit
2, 1
0
Bit
7
Bit Name
—
AF
Bit Name
PEF
Initial Value
0
0
Initial Value
0
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Alarm Flag
The AF flag is set to 1 when the alarm time set in
an alarm register (only registers with ENB bit of
the corresponding alarm registers and YAEN bit
in RCR3 set to 1) matches the clock and calendar
time. This flag is cleared to 0 when 0 is written,
but holds the previous value when 1 is written.
0: Clock/calendar and alarm register have not
1: [Setting condition] Clock/calendar and alarm
Description
Periodic Interrupt Flag
Indicates interrupt generation with the period
designated by the PES2 to PES0 bits. When set
to 1, PEF generates periodic interrupts.
0: Interrupts not generated with the period
1: [Setting condition] When interrupts are
matched.
[Clearing condition] When 0 is written to AF
register have matched (only registers that ENB
bit and YAEN bit is 1)
designated by the PES bits.
[Clearing condition] When 0 is written to PEF
generated with the period designated by the
PES bits or 1 is written to PEF