HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 394

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 14.7 shows an example of toggle output.
In this example TCNT has been designated as a periodic counter (with counter clearing performed
by compare match B), and settings have been made so that output is toggled by compare match A.
14.4.3
Buffer operation, enables TGRC and TGRD to be used as buffer registers.
Table 14.6 shows the register combinations used in buffer operation.
Table 14.6 Register Combinations in Buffer Operation
Timer General Register
TGRA
TGRB
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register. For update timing from a buffer register, rewriting on
compare match occurrence or on counter cleaning can be selected.
This operation is illustrated in figure 14.8.
Rev. 2.00, 09/03, page 346 of 690
Buffer Operation
Buffer register
BFWT bit
H'FFFF
H'0000
TO pin
TGRB
TGRA
Counter clearing signal
Figure 14.7 Example of Toggle Output Operation
TCNT value
Figure 14.8 Compare Match Buffer Operation
Compare match signal
Timer general
register
Counter cleared by TGRB compare match
Buffer Register
TGRC
TGRD
Comparator
Toggle output
Time
TCNT