HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 567

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 20.9 Port J Data Register (PJDR) Read/Write Operations
Note: n = 0 to 7
20.10
Port K is an 8-bit input/output port with the pin configuration shown in figure 20.10. Each pin has
an input pull-up MOS, which is controlled by the port K control register (PKCR) in the PFC.
20.10.1 Register Description
Port K has the following register. For details on the register address and access size, see section
24, List of Registers.
20.10.2 Port K Data Register (PKDR)
PKDR is an 8-bit readable/writable register that stores data for pins PTK7 to PTK0. Bits PK7DT
to PK0DT correspond to pins PTK7 to PTK0. When the pin function is general output port, if the
port is read, the value of the corresponding PKDR bit is returned directly. When the function is
general input port, if the port is read, the corresponding pin level is read.
PJnMD1 PJnMD0 Pin State
0
1
Port K data register (PKDR)
PJCR State
Port K
0
1
0
1
NF
Output
Setting
Prohibited
Setting
Prohibited
Port K
Figure 20.10 Port K
Read
PJDR value
PJDR value
PTK7 (input/output)/A25 (output)
PTK6 (input/output)/A24 (output)
PTK5 (input/output)/A23 (output)
PTK4 (input/output)/A22 (output)
PTK3 (input/output)/A21 (output)
PTK2 (input/output)/A20 (output)
PTK1 (input/output)/A19 (output)
PTK0 (input/output)/A0 (output)
Write
Data can be written to PJDR but no effect on
pin state.
Written data is output from the pin.
Rev. 2.00, 09/03, page 519 of 690