HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 461
HD6417705F133BV
Manufacturer Part Number
HD6417705F133BV
Description
MPU 3V 0K PB-FREE 208 FP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417705F133BV.pdf
(741 pages)
Specifications of HD6417705F133BV
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
105
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 461 of 741
- Download datasheet (5Mb)
In serial reception, the SCIF operates as described below.
1. The SCIF monitors the communication line, and if 0 of a start bit is detected, performs internal
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
Note: Reception continues when a receive error (a framing error or parity error) occurs.
4. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-data-full
synchronization and starts reception.
After receiving these bits, the SCIF carries out the following checks.
a. Stop bit check: the SCIF checks whether the stop bit is 1. If there are two stop bits, only the
b. The SCIF checks whether receive data can be transferred from the receive shift register
c. Break check: the SCIF checks that the BRK flag is 0, indicating that the break state is not
If all the above checks are passed, the receive data is stored in SCFRDR.
interrupt (RXI) request is generated.
If the ERIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt
(ERI) request is generated.
If the BRIE bit in SCSCR is set to 1 when the BRK flag changes to 1, a break reception
interrupt (BRI) request is generated.
If the DRIE bit in SCSCR is set to 1 when the DR flag changes to 1, a receive-data-ready
interrupt (DRI) request is generated.
The vectors of receive-FIFO-data-full and receive-data-ready interrupts are the same. The
vectors of receive-error and break reception interrupts are the same.
first is checked.
(SCRSR) to SCFRDR.
set.
Rev. 2.00, 09/03, page 413 of 690
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