HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 377

MPU 3V 0K PB-FREE 208 FP

HD6417705F133BV

Manufacturer Part Number
HD6417705F133BV
Description
MPU 3V 0K PB-FREE 208 FP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417705F133BV

Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
105
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises four 16-bit timer channels.
14.1
TIMTPU8A_000020020100
Maximum 4-pulse output
A total of 16 timer general registers (TGRA to TGRD 4 ch.) are provided (four each for
channels). TGRA can be set as an output compare register.
TGRB, TGRC, and TGRD for each channel can also be used as timer counter clearing
registers. TGRC and TGRD can also be used as buffer registers.
Selection of four counter input clocks for channels 0 to 3
The following operations can be set for each channel:
Waveform output at compare match: Selection of 0, 1, or toggle output
Counter clear operation: Counter clearing possible by compare match
PWM mode: Any PWM output duty cycle can be set
Buffer operation settable for each channel
Automatic rewriting of output compare register possible
An interrupt request for each channel
Compare match and overflow interrupt requests can be enabled or disabled for each source
independently
Features
Section 14 16-Bit Timer Pulse Unit (TPU)
Maximum of 4-phase PWM output possible
Rev. 2.00, 09/03, page 329 of 690

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