HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 472

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

d. Simultaneous Serial Data Transmission and Reception
Figure 16.16 shows sample flowcharts for simultaneous serial transmission and reception.
Rev. 2.00, 09/03, page 424 of 690
Figure 16.16 Sample Simultaneous Serial Transmission and Reception Flowchart (1)
Write remaining transmit data to SCFTDR
Set TE and RE bits in SCSCR
simultaneously
When using transmit FIFO data interrupt,
set TIE bit to 1
When using receive FIFO data interrupt,
set RIE bit to 1
Read receive trigger number of receive
Set receive trigger number in RTRG1
Clear TE and RE bits in SCSCR to 0
Read TDFE and RDF bits in SCSSR
SCSSR after reading 1 from them
Write 0 to TDFE and RDF bits in
data bytes from SCFRDR
and RTRG0 in SCFCR
transmission/reception
transmission/reception
Start of simultaneous
TDFE =1?
TDFE =1?
Yes
RDF =1?
RDF =1?
End of
Yes
(First Transfer after Initialization)
No
No
[1]
[2]
[3]
[4]
[1] Set the receive trigger number
[2] Write the remaining transmit data
[3] Transmission/reception is started
[4] After the end of transmission/reception,
in SCFCR.
to SCFTDR, and if there is receive
data in the FIFO, read receive data
until there is less than the receive
trigger setting number, read the
TDFE and RDF bits in SCSSR, and
if 1, clear to 0.
when the TE and RE bits in SCSCR
are set to 1. The TE and RE bits
must be set simultaneously.
clear the TE and RE bits to 0.