HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 431

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
5
4
Bit
Name
PE
O/E
Initial
Value
0
0
R/W
R/W
R/W
Description
Parity Enable
Selects whether or not parity bit addition is performed in
transmission, and parity bit checking in reception.
This setting is only valid in asynchronous mode. In
synchronous mode, parity bit addition and checking is
not performed, regardless of the PE setting.
0: Parity bit addition and checking disabled
1: Parity bit addition and checking enabled *
Note: * When the PE bit is set to 1, the parity (even or
Parity Mode
Selects either even or odd parity for use in parity
addition and checking. The O/E bit setting is only valid
when the PE bit is set to 1, enabling parity bit addition
and checking. The O/E bit setting is invalid when parity
addition and checking is disabled in asynchronous and
clock synchronous mode.
0: Even parity *
1: Odd parity *
Notes: 1. When even parity is set, parity bit addition is
odd) specified by the O/E bit is added to
transmit data before transmission. In reception,
the parity bit is checked for the parity (even or
odd) specified by the O/E bit.
2. When odd parity is set, parity bit addition is
performed in transmission so that the total
number of 1-bits in the transmit character
plus the parity bit is even. In reception, a
check is performed to see if the total
number of 1-bits in the receive character
plus the parity bit is even.
performed in transmission so that the total
number of 1-bits in the transmit character
plus the parity bit is odd. In reception, a
check is performed to see if the total
number of 1-bits in the receive character
plus the parity bit is odd.
2
1
Rev. 2.00, 09/03, page 383 of 690