HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 610

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.3.7
Break Condition Specified for an L Bus Instruction Fetch Cycle
1. Register specifications
2. Register specifications
Rev. 2.00, 09/03, page 562 of 690
BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010,
BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300400
Specified conditions: Channel A/channel B independent mode
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E,
BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000008, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B sequential mode
A user break occurs after an instruction of address H'00000404 is executed or before
instructions of addresses H'00008010 to H'00008016 are executed.
After an instruction with ASID = H'80 and address H'00037226 is executed, a user break
occurs before an instruction with ASID = H'70 and address H'0003722E is executed.
Usage Examples
Channel A
Address:
Bus cycle:
The ASID check is not included.
Channel B
Address:
Data:
Bus cycle:
The ASID check is not included.
Channel A
Address:
Bus cycle:
Channel B
Address:
Data:
Bus cycle:
H'00000404, Address mask: H'00000000
L bus/instruction fetch (after instruction execution)/read (operand size
is not included in the condition)
H'00008010, Address mask: H'00000006
H'00000000, Data mask: H'00000000
L bus/instruction fetch (before instruction execution)/read (operand size
is not included in the condition)
H'00037226, Address mask: H'00000000, ASID = H'80
L bus/instruction fetch (before instruction execution)/read/word
H'0003722E, Address mask: H'00000000, ASID = H'70
H'00000000, Data mask: H'00000000
L bus/instruction fetch (before instruction execution)/read/word