HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 23

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.2
5.3
5.4
Section 6 Interrupt Controller (INTC)............................................................ 125
6.1
6.2
6.3
6.4
6.5
6.6
Section 7 Bus State Controller (BSC) ............................................................ 149
7.1
5.1.3
5.1.4
5.1.5
Exception Handling Function ....................................................................................... 113
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Individual Exception Operations .................................................................................. 118
5.3.1
5.3.2
5.3.3
Usage Notes................................................................................................................. 124
Features ....................................................................................................................... 125
Input/Output Pins......................................................................................................... 127
Register Descriptions ................................................................................................... 127
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
Interrupt Sources.......................................................................................................... 136
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
Operation..................................................................................................................... 144
6.5.1
6.5.2
Usage Note .................................................................................................................. 147
Overview ..................................................................................................................... 149
7.1.1
7.1.2
Interrupt Event Register (INTEVT).................................................................. 111
Interrupt Event Register 2 (INTEVT2)............................................................. 112
Exception Address Register (TEA) .................................................................. 112
Exception Handling Flow ................................................................................ 113
Exception Vector Addresses ............................................................................ 114
Exception Codes.............................................................................................. 114
Exception Request and BL Bit (Multiple Exception Prevention)....................... 114
Exception Source Acceptance Timing and Priority........................................... 115
Resets.............................................................................................................. 118
General Exceptions.......................................................................................... 118
General Exceptions (MMU Exceptions)........................................................... 121
Interrupt Priority Level Setting Registers A to H (IPRA to IPRH)..................... 128
Interrupt Control Register 0 (ICR0).................................................................. 129
Interrupt Control Register 1 (ICR1).................................................................. 130
Interrupt Control Register 2 (ICR2).................................................................. 132
PINT Interrupt Enable Register (PINTER) ....................................................... 132
Interrupt Request Register 0 (IRR0) ................................................................. 133
Interrupt Request Register 1 (IRR1) ................................................................. 134
Interrupt Request Register 2 (IRR2) ................................................................. 135
NMI Interrupt.................................................................................................. 136
IRQ Interrupts ................................................................................................. 136
IRL Interrupts.................................................................................................. 137
PINT Interrupt................................................................................................. 138
On-Chip Peripheral Module Interrupts ............................................................. 138
Interrupt Exception Handling and Priority........................................................ 139
Interrupt Sequence........................................................................................... 144
Multiple Interrupts........................................................................................... 147
Features........................................................................................................... 149
Block Diagram ................................................................................................ 150
Rev. 2.00, 09/03, page xxi of xlvi