MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 481

• Manufacturer Part Number: MC9S12E128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 90
• Ram Memory Size: 8KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
CAPMOD
DBGBRK
Field
1:0
3
DBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint based
on comparator A and B to the CPU upon completion of a tracing session. Please refer to
“Breakpoints,” for further details.
0 CPU break request not enabled
1 CPU break request enabled
Capture Mode Field — See
automatically inhibit redundant entries into capture memory. In detail mode, the debugger is storing address and
data for all cycles except program fetch (P) and free (f) cycles. In profile mode, the debugger is returning the
address of the last instruction executed by the CPU on each access of trace buffer address. Refer to
Section 16.4.2.6, “Capture
Table 16-3. DBGC1 Field Descriptions (continued)
Modes,” for more information.
Table 16-4
CAPMOD
MC9S12E128 Data Sheet, Rev. 1.07
Table 16-4. CAPMOD Encoding
00
01
10
11
for capture mode field definitions. In LOOP1 mode, the debugger will
Description
Description
PROFILE
LOOP1
DETAIL
Normal
Chapter 16 Debug Module (DBGV1)
Section 16.4.3,
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