DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 1024

MCU 3V 384K 128-QFP

DF2367VF33

Manufacturer Part Number
DF2367VF33
Description
MCU 3V 384K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2367VF33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2367VF33
HD64F2367VF33

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
DF2367VF33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Appendix
Rev.6.00 Mar. 18, 2009 Page 964 of 980
REJ09B0050-0600
Instruction
LDC
@ERs,CCR
LDC
@ERs,EXR
LDC@(d:16,E
Rs),CCR
LDC@(d:16,E
Rs),EXR
LDC@(d:32,E
Rs),CCR
LDC@(d:32,E
Rs),EXR
LDC
@ERs+,CCR
LDC
@ERs+,EXR
LDC
@aa:16,CCR
LDC
@aa:16,EXR
LDC
@aa:32,CCR
LDC
@aa:32,EXR
LDM.L @SP+,
(ERn-ERn+1)
*
LDM.L @SP+,
(ERn-ERn+2)
*
LDM.L @SP+,
(ERn-ERn+3)
*
LDMAC
ERs,MACH
8
8
8
1
R:W 2nd R:W
R:W 2nd R:W
R:W 2nd R:W 3rd R:W
R:W 2nd R:W 3rd R:W
R:W 2nd R:W 3rd R:W 4th R:W 5th R:W
R:W 2nd R:W 3rd R:W 4th R:W 5th R:W
R:W 2nd R:W
R:W 2nd R:W
R:W 2nd R:W 3rd R:W
R:W 2nd R:W 3rd R:W
R:W 2nd R:W 3rd R:W 4th R:W
R:W 2nd R:W 3rd R:W 4th R:W
R:W 2nd R:W
R:W 2nd R:W
R:W 2nd R:W
R:W
NEXT
2
NEXT
NEXT
NEXT
NEXT
NEXT
NEXT
NEXT
1 state of
internal
operation
3
R:W EA
R:W EA
NEXT
NEXT
1 state of
internal
operation
1 state of
internal
operation
NEXT
NEXT
1 state of
internal
operation
1 state of
internal
operation
1 state of
internal
operation
4
R:W EA
R:W EA
R:W EA
R:W EA
R:W EA
R:W EA
NEXT
NEXT
R:W:M
Stack
(H) *
R:W:M
Stack
(H) *
R:W:M
Stack
(H) *
2
2
2
5
NEXT
NEXT
R:W EA
R:W EA
R:W
Stack (L)
*
R:W
Stack (L)
*
R:W
Stack (L)
*
2
2
2
6
R:W EA
R:W EA
7
8
9

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