DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 623

MCU 3V 384K 128-QFP

DF2367VF33

Manufacturer Part Number
DF2367VF33
Description
MCU 3V 384K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2367VF33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2367VF33
HD64F2367VF33

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14.3.8
SCMR selects Smart Card interface mode and its format.
Bit
7
to
4
3
2
1
0
Bit Name
SDIR
SINV
SMIF
Smart Card Mode Register (SCMR)
Initial Value
All 1
0
0
1
0
R/W
R/W
R/W
R/W
Section 14 Serial Communication Interface (SCI, IrDA)
Description
Reserved
These bits are always read as 1.
Smart Card Data Transfer Direction
Selects the serial/parallel conversion format.
0: LSB-first in transfer
1: MSB-first in transfer
The bit setting is valid only when the transfer
data format is 8 bits. For 7-bit data, LSB-first is
fixed.
Smart Card Data Invert
Specifies inversion of the data logic level. The
SINV bit does not affect the logic level of the
parity bit. To invert the parity bit, invert the O/E
bit in SMR.
0: TDR contents are transmitted as they are.
1: TDR contents are inverted before being
Reserved
This bit is always read as 1.
Smart Card Interface Mode Select
This bit is set to 1 to make the SCI operate in
Smart Card interface mode.
0: Normal asynchronous mode or clocked
1: Smart card interface mode
Receive data is stored as it is in RDR.
transmitted. Receive data is stored in inverted
form in RDR.
synchronous mode
Rev.6.00 Mar. 18, 2009 Page 563 of 980
REJ09B0050-0600

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