DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 297

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Bit
2
1
0
Bit Name
DTIE1A
DTIE0B
DTIE0A
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Data Transfer End Interrupt Enable 1A
Enables or disables an interrupt to the CPU or
DTC when transfer ends. When DTE1 is cleared
to 0 while this bit is set to 1, the DMAC regards
this as indicating the end of a transfer, and
issues a transfer end interrupt request to the
CPU or DTC.
A transfer end interrupt can be canceled either
by clearing the DTIE1A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE1 bit to 1.
Data Transfer Interrupt Enable 0B
Enables or disables an interrupt to the CPU or
DTC when transfer on channel 1 is interrupted.
When DTME0 is cleared to 0 while this bit is set
to 1, the DMAC regards this as indicating a
break in the transfer, and issues a transfer break
interrupt request to the CPU or DTC.
A transfer break interrupt can be canceled either
by clearing the DTIE0B bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the DTME0 bit to 1.
Data Transfer End Interrupt Enable 0A
Enables or disables an interrupt to the CPU or
DTC when transfer ends. When DTE0 is cleared
to 0 while this bit is set to 1, the DMAC regards
this as indicating the end of a transfer, and
issues a transfer end interrupt request to the
CPU or DTC.
A transfer end interrupt can be canceled either
by clearing the DTIE0A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE0 bit to 1.
Rev.6.00 Mar. 18, 2009 Page 237 of 980
Section 7 DMA Controller (DMAC)
REJ09B0050-0600