DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 964

MCU 3V 384K 128-QFP

DF2367VF33

Manufacturer Part Number
DF2367VF33
Description
MCU 3V 384K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2367VF33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2367VF33
HD64F2367VF33

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Part Number
Manufacturer
Quantity
Price
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
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135
Part Number:
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Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
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Section 25 Electrical Characteristics
(5) Timing of On-Chip Peripheral Modules
Table 25.10 Timing of On-Chip Peripheral Modules
Conditions: V
Item
I/O ports
PPG
TPU
8-bit timer
Rev.6.00 Mar. 18, 2009 Page 904 of 980
REJ09B0050-0600
Output data delay time
Pulse output delay time
Input data setup time
Input data hold time
Timer output delay time
Timer input setup time
Timer clock input setup time t
Timer clock
pulse width
Timer output delay time
Timer reset input setup time t
Timer clock input setup time t
Timer clock
pulse width
φ
DREQ0, DREQ1
φ = 8 MHz to 33 MHz, T
T
a
CC
= –40°C to +85°C (wide-range specifications)
= 3.0 V to 3.6 V, AV
Single-edge
specification
Both-edge
specification
Single-edge
specification
Both-edge
specification
Figure 25.27 DMAC DREQ Input Timing
a
CC
= –20°C to +75°C (regular specifications),
= 3.0 V to 3.6 V, V
Symbol Min
t
t
t
t
t
t
t
t
t
t
t
PWD
PRS
PRH
POD
TOCD
TICS
TCKS
TCKWH
TCKWL
TMOD
TMRS
TMCS
TMCWH
TMCWL
t
DRQS
25
25
25
25
1.5
2.5
25
25
1.5
2.5
t
DRQH
ref
= 3.0 V to AV
Max
40
40
40
40
ns
ns
ns
ns
ns
ns
ns
t
t
ns
ns
ns
t
t
Unit
cyc
cyc
cyc
cyc
CC
, V
Test Conditions
Figure 25.28
Figure 25.29
Figure 25.30
Figure 25.31
Figure 25.32
Figure 25.34
Figure 25.33
SS
= AV
SS
= 0 V,

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