DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 319

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

7.5.6
In normal mode, transfer is performed with channels A and B used in combination. Normal mode
can be specified by setting the FAE bit in DMABCRH to 1 and clearing the BLKE bit in
DMACRA to 0. In normal mode, MAR is updated after data transfer of a byte or word in response
to a single transfer request, and this is executed the number of times specified in ETCRA. The
transfer source is specified by MARA, and the transfer destination by MARB. Table 7.9
summarizes register functions in normal mode.
Table 7.9
Register
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be
set separately for MARA and MARB.
The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented by 1 each time
a transfer is performed, and when its value reaches H'0000 the DTE bit in DMABCRL is cleared
and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this time, an interrupt request is sent
to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.
Figure 7.11 illustrates operation in normal mode.
23
23
15
Normal Mode
ETCRA
MARA
MARB
Register Functions in Normal Mode
0
0
0
Function
Source address
register
Destination
address register
Transfer counter Number of transfers Decremented every
Initial Setting
Start address of
transfer source
Start address of
transfer destination
Rev.6.00 Mar. 18, 2009 Page 259 of 980
Section 7 DMA Controller (DMAC)
Operation
Incremented/decremented
every transfer, or fixed
Incremented/decremented
every transfer, or fixed
transfer; transfer ends
when count reaches
H'0000
REJ09B0050-0600