DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 891

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Section 23 Power-Down Modes
When the STBY pin level is driven low, a transition is made to hardware standby mode.
23.2.3
Software Standby Mode
Transition to Software Standby Mode: If a SLEEP instruction is executed when the SSBY bit in
SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral
functions, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM
data, and the states of on-chip peripheral functions other than the SCI and A/D converter, and I/O
ports, are retained. Whether the address bus and bus control signals are placed in the high-
impedance state or retain the output state can be specified by the OPE bit in SBYCR.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
Clearing Software Standby Mode: Software standby mode is cleared by an external interrupt
(NMI pin, or pins IRQ0 to IRQ7), or by means of the RES pin or STBY pin. Setting the SSI bit in
SSIER to 1 enables IRQ0 to IRQ7 to be used as software standby mode clearing sources.
Clearing with an Interrupt:
When an NMI or IRQ0 to IRQ7 interrupt request signal is input, clock oscillation starts, and after
the elapse of the time set in bits STS3 to STS0 in SBYCR, stable clocks are supplied to the entire
LSI, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ7 interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ7 is
generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU
side or has been designated as a DTC activation source.
Clearing with the RES Pin:
When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation
starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low until clock
oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling.
Clearing with the STBY Pin:
When the STBY pin is driven low, a transition is made to hardware standby mode.
Rev.6.00 Mar. 18, 2009 Page 831 of 980
REJ09B0050-0600