DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 496

MCU 3V 384K 128-QFP

DF2367VF33

Manufacturer Part Number
DF2367VF33
Description
MCU 3V 384K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2367VF33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2367VF33
HD64F2367VF33

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Manufacturer
Quantity
Price
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Manufacturer:
Renesas Electronics America
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Manufacturer:
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Section 10 16-Bit Timer Pulse Unit (TPU)
Note:
Rev.6.00 Mar. 18, 2009 Page 436 of 980
REJ09B0050-0600
Bit
1
0
*
Bit
Name
TGFB
TGFA
Only 0 can be written, for flag clearing.
Initial value
0
0
R/W
R/(W) *
R/(W) *
Description
Input Capture/Output Compare Flag B
Status flag that indicates the occurrence of TGRB
input capture or compare match.
[Setting conditions]
[Clearing conditions]
Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA
input capture or compare match.
[Setting conditions]
[Clearing conditions]
When TCNT = TGRB while TGRB is functioning
as output compare register
When TCNT value is transferred to TGRB by
input capture signal while TGRB is functioning
as input capture register
When DTC is activated by TGIB interrupt while
DISEL bit of MRB in DTC is 0
When 0 is written to TGFB after reading TGFB
= 1
When TCNT = TGRA while TGRA is functioning
as output compare register
When TCNT value is transferred to TGRA by
input capture signal while TGRA is functioning
as input capture register
When DTC is activated by TGIA interrupt while
DISEL bit of MRB in DTC is 0
When 0 is written to TGFA after reading TGFA
= 1
When DMAC is activated by TGIA interrupt
while DTE bit of DMABCR in DMAC is set to 1

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