DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 513

MCU 3V 384K 128-QFP

DF2367VF33

Manufacturer Part Number
DF2367VF33
Description
MCU 3V 384K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2367VF33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2367VF33
HD64F2367VF33

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Part Number
Manufacturer
Quantity
Price
Part Number:
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Manufacturer:
Renesas Electronics America
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135
Part Number:
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Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
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Examples of Cascaded Operation: Figure 10.18 illustrates the operation when counting upon
TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been
designated as input capture registers, and the TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
Figure 10.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been
set for TCNT_1, and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCNT_1
clock
TCNT_1
TCNT_2
clock
TCNT_2
TIOCA1,
TIOCA2
TGRA_1
TGRA_2
TCLKC
TCLKD
TCNT_2
TCNT_1
H'FFFF
H'03A1
Figure 10.18 Example of Cascaded Operation (1)
Figure 10.19 Example of Cascaded Operation (2)
FFFD
0000
FFFE
FFFF
0000
H'0000
0001
Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Mar. 18, 2009 Page 453 of 980
H'03A2
H'03A2
H'0000
0001
0002
0001
0000
H'0001
REJ09B0050-0600
FFFF
0000

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