DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 879

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

2. A value is set in bits STS3 to STS0 to give the specified transition time.
3. The target value is set in bits STC1 and STC0, and a transition is made to software standby
4. The clock pulse generator stops and the value set in STC1 and STC0 becomes valid.
5. Software standby mode is cleared, and a transition time is secured in accordance with the
6. After the set transition time has elapsed, this LSI resumes operation using the target
When STCS = 1, this LSI operates using the new multiplication factor immediately after bits
STC1 and STC0 are rewritten.
22.4
The frequency divider divides the PLL output clock to generate a 1/2 or 1/4 clock.
22.5
22.5.1
1. The following points should be noted since the frequency of φ changes according to the setting
2. All the on-chip peripheral modules operate on the φ. Therefore, note that the time processing
3. Note that the frequency of φ will be changed when setting SCKCR or PLLCR while executing
Note: * 34 MHz for the H8S/2368 0.18μm F-ZTAT Group
mode.
setting in STS3 to STS0.
multiplication factor.
of SCKCR and PLLCR.
Select the clock division ratio that is within the operation guaranteed range of clock cycle time
tcyc shown in the AC timing of Electrical Characteristics. In other words, the range of φ must
be specified from 8 MHz (min) to 33 MHz* (max); outside of this range must be prevented.
of modules such as a timer and SCI differ before and after changing the clock division ratio. In
addition, wait time for clearing software standby mode differs by changing the clock division
ratio. See the description, Setting Oscillation Stabilization Time after Clearing Software
Standby Mode in section 23.2.3, Software Standby Mode, for details.
the external bus cycle with the write-data-buffer function.
Frequency Divider
Usage Notes
Notes on Clock Pulse Generator
Rev.6.00 Mar. 18, 2009 Page 819 of 980
Section 22 Clock Pulse Generator
REJ09B0050-0600