DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 456
![MCU 3V 384K 128-QFP](/photos/28/61/286109/128-bfqfp_sml.jpg)
DF2367VF33
Manufacturer Part Number
DF2367VF33
Description
MCU 3V 384K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2368VTE34V.pdf
(1044 pages)
Specifications of DF2367VF33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2367VF33
HD64F2367VF33
HD64F2367VF33
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
DF2367VF33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 9 I/O Ports
9.14.2
PGDR stores output data for the port G pins.
9.14.3
PORTG shows port G pin states.
PORTG cannot be modified.
Note:
Rev.6.00 Mar. 18, 2009 Page 396 of 980
REJ09B0050-0600
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
*
Bit Name
—
PG6DR
PG5DR
PG4DR
PG3DR
PG2DR
PG1DR
PG0DR
Bit Name
—
PG6
PG5
PG4
PG3
PG2
PG1
PG0
Port G Data Register (PGDR)
Port G Register (PORTG)
Determined by the states of pins PG6 to PG0.
— *
— *
— *
— *
— *
— *
— *
Initial Value
0
0
0
0
0
0
0
0
Initial Value
Undefined
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R
R
R
R
R
R
R
Description
Reserved
This bit is always read as 0, and cannot be
modified.
An output data for a pin is stored when the pin
function is specified to a general purpose I/O.
Description
Reserved
If this bit is read, it will return an undefined value.
If a port G read is performed while PGDDR bits are
set to 1, the PGDR values are read. If a port G read
is performed while PGDDR bits are cleared to 0, the
pin states are read.
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