DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 302

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Section 7 DMA Controller (DMAC)
7.4.1
An interrupt request selected as a DMAC activation source can also simultaneously generate an
interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller.
With activation by an internal interrupt request, the DMAC accepts the interrupt request
independently of the interrupt controller. Consequently, interrupt controller priority settings are
irrelevant.
If the DMAC is activated by a CPU interrupt source or an interrupt request that is not used as a
DTC activation source (DTA = 1), the interrupt request flag is cleared automatically by the DMA
transfer. With ADI, TXI and RXI interrupts, however, the interrupt source flag is not cleared
unless the relevant register is accessed in a DMA transfer. If the same interrupt is used as an
activation source for more than one channel, the interrupt request flag is cleared when the highest-
priority channel is activated. Transfer requests for other channels are held pending in the DMAC,
and activation is carried out in order of priority.
When DTE = 0 after completion of a transfer, an interrupt request from the selected activation
source is not sent to the DMAC, regardless of the DTA bit setting. In this case, the relevant
interrupt request is sent to the CPU or DTC.
In case of overlap with a CPU interrupt source or DTC activation source (DTA = 0), the interrupt
request flag is not cleared by the DMAC.
7.4.2
If an external request (DREQ pin) is specified as a DMAC activation source, the relevant port
should be set to input mode in advance*. Level sensing or edge sensing can be used for external
requests.
External request operation in normal mode of short address mode or full address mode is
described below.
When edge sensing is selected, a byte or word is transferred each time a high-to-low transition is
detected on the DREQ pin. The next data transfer may not be performed if the next edge is input
before data transfer is completed.
When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is
held high. While the DREQ pin is held low, transfers continue in succession, with the bus being
released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a
transfer, the transfer is interrupted and the DMAC stands by for a transfer request.
Rev.6.00 Mar. 18, 2009 Page 242 of 980
REJ09B0050-0600
Activation by Internal Interrupt Request
Activation by External Request