DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 710

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Section 15 I
15.4.5
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to
figures 15.11 and 15.12. The reception procedure and operations in slave receive mode are
described below.
1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
2. When the slave address matches in the first frame following detection of the start condition,
Rev.6.00 Mar. 18, 2009 Page 650 of 980
REJ09B0050-0600
(master output)
(master output)
(slave output)
(slave output)
processing
bits in ICCRA to 1. (Initial setting) Set the MST and TRS bits in ICCRA to select slave receive
mode, and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read) and RDRF
is cleared. (Since the read data show the slave address and R/W, it is not used.)
ICDRR
ICDRT
ICDRS
TDRE
TEND
SCL
SDA
SDA
SCL
User
TRS
Slave Receive Operation
2
C Bus Interface2 (IIC2) (Option)
Figure 15.10 Slave Transmit Mode Operation Timing 2
9
A
Bit 7
1
Bit 6
2
Bit 5
3
Data n
Bit 4
[3] Clear TEND
4
Bit 3
5
Bit 2
6
[4] Read ICDRR (dummy read)
Bit 1
Slave transmit mode
after clearing TRS
7
Bit 0
8
9
A
[5] Clear TDRE
Slave receive
mode