DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 617

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Bit
5
4
Bit Name
ORER
FER
Initial Value
0
0
R/W
R/(W) *
R/(W) *
Section 14 Serial Communication Interface (SCI, IrDA)
Description
Overrun Error
Indicates that an overrun error occurred while
receiving and the reception has ended
abnormally.
[Setting condition]
When the next serial reception is completed
while RDRF = 1
The receive data prior to the overrun error is
retained in RDR, and the data received
subsequently is lost. Also, subsequent serial
reception cannot be continued while the ORER
flag is set to 1. In clocked synchronous mode,
serial transmission cannot be continued, either.
[Clearing condition]
When 0 is written to ORER after reading ORER =
1
The ORER flag is not affected and retains its
previous state when the RE bit in SCR is cleared
to 0.
Framing Error
Indicates that a framing error occurred while
receiving in asynchronous mode and the
reception has ended abnormally.
[Setting condition]
When the stop bit is 0
In 2-stop-bit mode, only the first stop bit is
checked for a value of 0; the second stop bit is
not checked. If a framing error occurs, the
receive data is transferred to RDR but the RDRF
flag is not set. Also, subsequent serial reception
cannot be continued while the FER flag is set to
1. In clocked synchronous mode, serial
transmission cannot be continued, either.
[Clearing condition]
When 0 is written to FER after reading FER = 1
The FER flag is not affected and retains its
previous state when the RE bit in SCR is cleared
to 0.
Rev.6.00 Mar. 18, 2009 Page 557 of 980
REJ09B0050-0600