DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 719

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Table 15.4 Time for monitoring SCL
CKS3
1
Note:
15.7
1. Issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed.
2. Control WAIT in the I
0
Check SCLO in the I
When the start/stop conditions are issued (retransmitted) at the specific timing under the
following condition (i) or (ii), such conditions may not be output successfully. This does not
occur in other cases.
(i) When the rising of SCL falls behind the time specified in section 15.6, Bit Synchronous
(ii) When the bit synchronous circuit is activated by extending the low period of eighth and
When WAIT is set to 1, and SCL is driven low for two or more transfer clocks by the slave
device at the eighth and ninth clocks, the high period of ninth clock may be shortened. This
does not occur in other cases.
Circuit, by the load of the SCL bus (load capacitance or pull-up resistance)
ninth clocks, that is driven by the slave device
*
Usage Notes
If the operating frequency exceeds 20 MHz, it may not be possible to maintain the
prescribed transfer rate under certain load conditions. A setting other than 7.5 tcyc
should therefore be used.
SCL monitor
timing reference
clock
Internal SCL
CKS2
0
1
0
1
SCL
Figure 15.18 Timing of the Bit Synchronous Circuit
2
C control register B (ICCRB)* to confirm the fall of the ninth clock.
2
C bus mode register (ICMR) to be set to 0.
17.5 tcyc
41.5 tcyc
Time for monitoring SCL
7.5 tcyc *
19.5 tcyc
VIH
Section 15 I
Rev.6.00 Mar. 18, 2009 Page 659 of 980
2
C Bus Interface2 (IIC2) (Option)
REJ09B0050-0600