DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 669

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

4. Transmission of one frame, including a retransfer, is judged to have been completed, and the
Figure 14.28 shows a flowchart for transmission. The sequence of transmit operations can be
performed automatically by specifying the DTC or DMAC to be activated with a TXI interrupt
source. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in
SSR, and a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If the TXI
request is designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will
be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE
and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC or
DMAC. In the event of an error, the SCI retransmits the same data automatically. During this
period, the TEND flag remains cleared to 0 and the DTC or DMAC is not activated. Therefore,
the SCI and DTC or DMAC will automatically transmit the specified number of bytes in the event
of an error, including retransmission. However, the ERS flag is not cleared automatically when an
error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be
generated in the event of an error, and the ERS flag will be cleared.
When performing transfer using the DTC or DMAC, it is essential to set and enable the DTC or
DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures,
refer to section 8, Data Transfer Controller (DTC) or section 7, DMA Controller (DMAC).
TDRE
TEND
FER/ERS
TEND bit in SSR is set to 1. If the TIE bit in SCR is set at this time, a TXI interrupt request is
generated. Writing transmit data to TDR transfers the next transmit data.
Ds
Transfer to TSR from TDR
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Figure 14.26 Retransfer Operation in SCI Transmit Mode
nth transfer frame
[6]
Section 14 Serial Communication Interface (SCI, IrDA)
[7]
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer to TSR from TDR
Retransferred frame
Rev.6.00 Mar. 18, 2009 Page 609 of 980
(DE)
[8]
[9]
REJ09B0050-0600
Ds D0 D1 D2 D3 D4
Transfer to TSR
Transfer
frame n+1
from TDR