DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 822

MCU 3V 384K 128-QFP

DF2367VF33

Manufacturer Part Number
DF2367VF33
Description
MCU 3V 384K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2367VF33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2367VF33
HD64F2367VF33

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
DF2367VF33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 20 Flash Memory (0.18-μm F-ZTAT Version)
(3)
The procedures for download, initialization, and erasing are shown in figure 20.12.
The procedure program must be executed in an area other than the user MAT to be erased.
Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the
on-chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 20.4.4, Procedure Program and Storable Area for
Programming Data.
For the downloaded on-chip program area, refer to figure 20.10.
Rev.6.00 Mar. 18, 2009 Page 762 of 980
REJ09B0050-0600
Erasing Procedure in User Program Mode
Set the FPEFEQ, FUBRA
JSR FTDAR setting + 32
Select on-chip program
to be downloaded and
Start erasing procedure
destination by FTDAR
specify download
Set SCO to 1 and
execute download
Set FKEY to H'A5
Clear FKEY to 0
Initialization
FPFR = 0 ?
DPFR = 0?
parameters
program
a
Yes
Yes
Initialization error processing
Download error processing
No
No
1.
Figure 20.12 Erasing Procedure
No
JSR FTDAR setting + 16
Disable interrupts and
bus master operation
Set FEBS parameter
procedure program
Set FKEY to H'5A
Clear FKEY to 0
other than CPU
Required block
End erasing
FPFR = 0?
completed?
erasing is
Erasing
a
Yes
Yes
Clear FKEY and erasing
No
error processing
2.
3.
4.
5.
6.

Related parts for DF2367VF33