C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 103
C8051F302
Manufacturer Part Number
C8051F302
Description
IC 8051 MCU 8K FLASH 11MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F30xr
Specifications of C8051F302
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
11-VQFN
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SMBus, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
8
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F302-GMR
Manufacturer:
SiliconL
Quantity:
3 000
Company:
Part Number:
C8051F302-GMR
Manufacturer:
SILICON
Quantity:
5 000
Part Number:
C8051F302-GMR
Manufacturer:
SILICONLABS/芯科
Quantity:
20 000
13.
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Manage-
ment Bus Specification, version 1.1, and compatible with the I
system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data.
Data can be transferred at up to 1/10th of the system clock operating as master or slave (this can be faster than
allowed by the SMBus specification, depending on the system clock used). A method of extending the clock-low
duration is available to accommodate devices with different speed capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple masters. The
SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic,
and START/STOP control and generation. Three SFRs are associated with the SMBus: SMB0CF configures the
SMBus; SMB0CN controls the status of the SMBus; and SMB0DAT is the data register, used for both transmitting
and receiving SMBus data and slave addresses.
M
R
A
S
T
E
Interrupt
Request
SMBUS
M
X
O
D
E
T
SMB0CN
S
T
A
O
S
T
A
C
K
R
Q
O
A
R
B
S
T
L
A
C
K
S
I
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
IRQ Generation
SMBUS CONTROL LOGIC
M
E
N
S
B
N
H
I
Figure 13.1. SMBus Block Diagram
SMB0CF
B
U
S
Y
E
X
T
H
O
D
L
M
O
S
B
T
E
7
M
S
B
F
T
E
6
SMB0DAT
S
M
B
C
S
1
5
M
S
B
C
S
0
4
Data Path
3
Control
2
1
0
00
01
10
11
Rev. 2.3
Control
Control
SDA
SCL
2
C serial bus. Reads and writes to the interface by the
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
FILTER
FILTER
C8051F300/1/2/3/4/5
N
N
SDA
SCL
C
R
O
R
S
S
B
A
Port I/O
103