C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 108

• Manufacturer Part Number: C8051F302
• Description: IC 8051 MCU 8K FLASH 11MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F302

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-VQFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

C8051F300/1/2/3/4/5
13.4.1. SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the
SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is
enabled for all master and slave events. Slave events may be disabled by setting the INH bit. With slave events inhib-
ited, the SMBus interface will still monitor the SCL and SDA pins; however, the interface will NACK all received
addresses and will not generate any slave interrupts. When the INH bit is set, all slave events will be inhibited follow-
ing the next START (interrupts will continue for the duration of the current transfer).
The SMBCS1-0 bits select the SMBus clock source, which is used only when operating as a master or when the Free
Timeout detection is enabled. When operating as a master, overflows from the selected source determine the absolute
minimum SCL low and high times as defined in Equation 13.1. Note that the selected clock source may be shared by
other peripherals so long as the timer is left running at all times. For example, Timer 1 overflows may generate the
SMBus and UART baud rates simultaneously. Timer configuration is covered in
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 13.1. When the interface is operating as a master (and SCL is not driven or extended by any other devices
on the bus), the typical SMBus bit rate is approximated by Equation 13.2.
Figure 13.4 shows the typical SCL generation described by Equation 13.2. Notice that T
large as T
slave devices, or driven low by contending master devices). The bit rate when operating as a master will never exceed
the limits defined by equation Equation 13.1.
108
Timer Source
Overflows
LOW
SCL
. The actual SCL output may vary due to other devices on the bus (SCL may be extended low by slower
T
Equation 13.1. Minimum SCL High and Low Times
Low
T
Figure 13.4. Typical SMBus SCL Generation
Table 13.1. SMBus Clock Source Selection
HighMin
SMBCS1 SMBCS0 SMBus Clock Source
Equation 13.2. Typical SMBus Bit Rate
0
0
1
1
BitRate
=
T
High
T
LowMin
0
1
0
1
=
f
--------------------------------------------- -
Rev. 2.3
ClockSourceOverflow
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
=
--------------------------------------------- -
f
ClockSourceOverflow
3
1
SCL High Timeout
Section “15. Timers” on page
HIGH
is typically twice as
133.