C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 14
![IC 8051 MCU 8K FLASH 11MLP](/photos/16/12/161294/c8051f300_sml.jpg)
C8051F302
Manufacturer Part Number
C8051F302
Description
IC 8051 MCU 8K FLASH 11MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F30xr
Specifications of C8051F302
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
11-VQFN
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SMBus, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
8
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F302-GMR
Manufacturer:
SiliconL
Quantity:
3 000
Company:
Part Number:
C8051F302-GMR
Manufacturer:
SILICON
Quantity:
5 000
Part Number:
C8051F302-GMR
Manufacturer:
SILICONLABS/芯科
Quantity:
20 000
C8051F300/1/2/3/4/5
1.1.
1.1.1. Fully 8051 Compatible
The C8051F300/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully
compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop
software. The CIP-51 core offers all the peripherals included with a standard 8052, including two standard 16-bit
counter/timers, one enhanced 16-bit counter/timer with external oscillator input, a full-duplex UART with extended
baud rate configuration, 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space, and a
byte-wide I/O Port.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to exe-
cute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in
one or two system clock cycles, with only four instructions taking more than four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instrutions that require each
execution time.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.3 shows a com-
parison of peak throughputs for various 8-bit microcontroller cores with their maximum system clocks.
14
Number of Instructions
Clocks to Execute
CIP-51™ Microcontroller Core
Figure 1.3. Comparison of Peak MCU Execution Speeds
25
20
15
10
5
26
1
(25MHz clk)
CIP-51
Cygnal
50
2
(33MHz clk)
2/3
PIC17C75x
Rev. 2.3
5
Microchip
14
3
(33MHz clk)
Philips
80C51
3/4
7
4
3
(16MHz clk)
ADuC812
8051
4/5
1
5
2
8
1