C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 24

• Manufacturer Part Number: C8051F302
• Description: IC 8051 MCU 8K FLASH 11MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F302

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-VQFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

C8051F300/1/2/3/4/5
4.
24
Pin Number
10
11
1
2
3
4
5
6
7
8
9
PINOUT AND PACKAGE DEFINITIONS
CNVSTR
XTAL1 /
XTAL2 /
Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5
VREF /
C2CK /
Name
C2D /
P0.6 /
VDD
GND
/RST
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.7
Type
A In
D I/O or
A In
D I/O or
A In
A In
D I/O or
A In
A Out
D I/O
D I/O or
A In
D I/O or
A In
D I/O
D I/O
D I/O or
A In
D I/O
D I/O
D I/O or
A In
Description
External Voltage Reference Input.
Port 0.0. See
Port 0.1. See
Power Supply Voltage.
Crystal Input. This pin is the external oscillator circuit return for a
crystal or ceramic resonator. See
Port 0.2. See
Crystal Input/Output. For an external crystal or resonator, this pin
is the excitation driver. This pin is the external clock input for
CMOS, capacitor, or RC network configurations. See
11.2.
Port 0.3. See
Port 0.4. See
Port 0.5. See
Clock signal for the C2 Development Interface.
Device Reset. Open-drain output of internal POR or VDD moni-
tor. An external source can initiate a system reset by driving this
pin low for at least 10 µs.
Port 0.6. See
ADC External Convert Start Input Strobe.
Data signal for the C2 Development Interface.
Port 0.7. See
Ground.
Rev. 2.3
Section 12
Section 12
Section 12
Section 12
Section 12
Section 12
Section 12
Section 12
for complete description.
for complete description.
for complete description.
for complete description.
for complete description.
for complete description.
for complete description.
for complete description.
Section
11.2.
Section