C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 55

IC 8051 MCU 8K FLASH 11MLP

C8051F302

Manufacturer Part Number
C8051F302
Description
IC 8051 MCU 8K FLASH 11MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F30xr
Datasheets

Specifications of C8051F302

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
11-VQFN
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SMBus, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
8
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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8.1.
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set.
Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the
binary and functional equivalent of their MCS-51™ counterparts, including opcodes, addressing modes and effect on
PSW flags. However, instruction timing is different than that of the standard 8051.
8.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles
varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle tim-
ing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as there
are program bytes in the instruction. Conditional branch instructions take one less clock cycle to complete when the
branch is not taken as opposed to when the branch is taken. Table 8.1 is the CIP-51 Instruction Set Summary,
which includes the mnemonic, number of bytes, and number of clock cycles for each instruction.
8.1.2. MOVX Instruction and Program Memory
The MOVX instruction is typically used to access external data memory (Note: the C8051F300/1/2/3/4/5 does not
support external data or program memory). In the CIP-51, the MOVX instruction accesses the on-chip program mem-
ory space implemented as re-programmable FLASH memory. This feature provides a mechanism for the CIP-51 to
update program code and use the program memory space for non-volatile data storage. Refer to
Memory” on page 83
Mnemonic
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
INSTRUCTION SET
for further details.
Table 8.1. CIP-51 Instruction Set Summary
Description
Add register to A
Add direct byte to A
Add indirect RAM to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect RAM to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment direct byte
Increment indirect RAM
Decrement A
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
ARITHMETIC OPERATIONS
Rev. 2.3
C8051F300/1/2/3/4/5
Bytes
Section “10. FLASH
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
Cycles
Clock
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
2
2
1
55

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