C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 116

• Manufacturer Part Number: C8051F302
• Description: IC 8051 MCU 8K FLASH 11MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F302

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-VQFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

C8051F300/1/2/3/4/5
13.5.2. Master Receiver Mode
Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START
condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case
the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the slave on SDA while the
SMBus outputs the serial clock. The slave transmits one or more bytes of serial data. After each byte is received,
ACKRQ is set to ‘1’ and an interrupt is generated. Software must write the ACK bit (SMB0CN.1) to define the out-
going acknowledge value (Note: writing a ‘1’ to the ACK bit generates an ACK; writing a ‘0’ generates a NACK).
Software should write a ‘0’ to the ACK bit after the last byte is received, to transmit a NACK. The interface exits
Master Receiver Mode after the STO bit is set and a STOP is generated. Note that the interface will switch to Master
Transmitter Mode if SMB0DAT is written while an active Master Receiver. Figure 13.9 shows a typical Master
Receiver sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the
‘data byte transferred’ interrupts occur before the ACK cycle in this mode.
116
Interrupt
S
Figure 13.9. Typical Master Receiver Sequence
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
R
Interrupt
A
Data Byte
Rev. 2.3
Interrupt
A
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Data Byte
Interrupt
N
P