C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 110

• Manufacturer Part Number: C8051F302
• Description: IC 8051 MCU 8K FLASH 11MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F302

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-VQFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

C8051F300/1/2/3/4/5
110
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bits1-0:
ENSMB
R/W
Bit7
ENSMB: SMBus Enable.
This bit enables/disables the SMBus interface. When enabled, the interface constantly monitors the
SDA and SCL pins.
0: SMBus interface disabled.
1: SMBus interface enabled.
INH: SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events occur.
This effectively removes the SMBus slave from the bus. Master Mode interrupts are not affected.
0: SMBus Slave Mode enabled.
1: SMBus Slave Mode inhibited.
BUSY: SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0 when a
STOP or free-timeout is sensed.
EXTHOLD: SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to Table 13.2.
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
SMBTOE: SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 2 to reload
while SCL is high and allows Timer 2 to count when SCL goes low. Timer 2 should be programmed
to generate interrupts at 25 ms, and the Timer 2 interrupt service routine should reset SMBus commu-
nication.
SMBFTE: SMBus Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for more
than 10 SMBus clock source periods.
SMBCS1-SMBCS0: SMBus Clock Source Selection.
These two bits select the SMBus clock source, which is used to generate the SMBus bit rate. The
selected device should be configured according to Equation 13.1.
SMBCS1
INH
R/W
Bit6
Figure 13.5. SMB0CF: SMBus Clock/Configuration Register
0
0
1
1
SMBCS0 SMBus Clock Source
BUSY
Bit5
R
0
1
0
1
EXTHOLD SMBTOE SMBFTE
R/W
Bit4
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
Timer 0 Overflow
Timer 1 Overflow
Rev. 2.3
R/W
Bit3
R/W
Bit2
SMBCS1
R/W
Bit1
SMBCS0
R/W
Bit0
SFR Address:
00000000
Reset Value
0xC1