C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 53

IC 8051 MCU 8K FLASH 11MLP

C8051F302

Manufacturer Part Number
C8051F302
Description
IC 8051 MCU 8K FLASH 11MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F30xr
Datasheets

Specifications of C8051F302

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
11-VQFN
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SMBus, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
8
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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8.
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™
instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has
a superset of all the peripherals included with a standard 8051. Included are three 16-bit counter/timers (see descrip-
tion in
128 byte Special Function Register (SFR) address space
in
directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a
single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional
custom peripherals and functions to extend its capability (see Figure 8.1 for a block diagram). The CIP-51 includes
the following features:
-
-
-
-
-
Section
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
256 Bytes of Internal RAM
Byte-Wide I/O Port
Section
CIP-51 MICROCONTROLLER
12). The CIP-51 also includes on-chip debug hardware (see description in
15), an enhanced full-duplex UART (see description in
RESET
CLOCK
STOP
IDLE
ACCUMULATOR
PROGRAM COUNTER (PC)
CONTROL
PSW
PRGM. ADDRESS REG.
LOGIC
Figure 8.1. CIP-51 Block Diagram
POWER CONTROL
PC INCREMENTER
DATA POINTER
REGISTER
BUFFER
TMP1
PIPELINE
ALU
TMP2
DATA BUS
DATA BUS
D8
D8
D8
(Section
Rev. 2.3
-
-
-
-
-
A16
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
D8
D8
D8
D8
B REGISTER
8.2.6), and one byte-wide I/O Port (see description
REGISTER
ADDRESS
INTERFACE
INTERFACE
INTERRUPT
INTERFACE
MEMORY
SRAM
SFR
BUS
C8051F300/1/2/3/4/5
Section
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
(256 X 8)
SFR_READ_DATA
SRAM
MEM_CONTROL
EMULATION_IRQ
MEM_ADDRESS
SFR_CONTROL
SFR_ADDRESS
SYSTEM_IRQs
14), 256 bytes of internal RAM,
Section
17), and interfaces
53

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